mediatek: Migrate to new interfaces
authorAntonio Nino Diaz <[email protected]>
Mon, 24 Sep 2018 16:15:54 +0000 (17:15 +0100)
committerAntonio Nino Diaz <[email protected]>
Fri, 28 Sep 2018 14:34:17 +0000 (15:34 +0100)
- mt6795: Migrate to new GIC interfaces.
- Remove support for PSCI platform compatibility layer.
- Migrate to bl31_early_platform_setup2().
- Migrate from cm_init_context() to cm_init_my_context().
- Use PLAT_VIRT_ADDR_SPACE_SIZE and PLAT_PHY_ADDR_SPACE_SIZE.
- Update Makefile paths.
- Use private definition of bl31_params_t.

This is an incomplete migration, mt6795 doesn't currently compile.

Change-Id: Icf9307637066cd6f2166524715e4f117f5ce2350
Signed-off-by: Antonio Nino Diaz <[email protected]>
16 files changed:
plat/mediatek/common/mtk_plat_common.c
plat/mediatek/common/mtk_plat_common.h
plat/mediatek/mt6795/bl31_plat_setup.c
plat/mediatek/mt6795/include/plat_macros.S
plat/mediatek/mt6795/include/platform_def.h
plat/mediatek/mt6795/plat_mt_gic.c
plat/mediatek/mt6795/plat_pm.c
plat/mediatek/mt6795/platform.mk
plat/mediatek/mt8173/aarch64/plat_helpers.S
plat/mediatek/mt8173/aarch64/platform_common.c
plat/mediatek/mt8173/bl31_plat_setup.c
plat/mediatek/mt8173/include/platform_def.h
plat/mediatek/mt8173/plat_mt_gic.c
plat/mediatek/mt8173/plat_pm.c
plat/mediatek/mt8173/plat_topology.c
plat/mediatek/mt8173/platform.mk

index a15131da228c9858f502132d7bc39a7a7cd94eb6..bff83c7343cf440f13b2f34de19b3f4da09dc690 100644 (file)
@@ -4,7 +4,6 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 #include <arch_helpers.h>
-#include <arm_gic.h>
 #include <bl_common.h>
 #include <cci.h>
 #include <console.h>
index 501c339bada787d92824a1a68b228b089276916c..923cf6932c372f02fd8b728e5fc884b53ce63359 100644 (file)
@@ -1,11 +1,15 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef __MTK_PLAT_COMMON_H__
 #define __MTK_PLAT_COMMON_H__
+
+#include <bl_common.h>
+#include <param_header.h>
 #include <stdint.h>
+
 /*******************************************************************************
  * Function and variable prototypes
  ******************************************************************************/
@@ -45,6 +49,15 @@ struct mtk_bl_param_t {
        uint64_t tee_info_addr;
 };
 
+struct mtk_bl31_params {
+       param_header_t h;
+       image_info_t *bl31_image_info;
+       entry_point_info_t *bl32_ep_info;
+       image_info_t *bl32_image_info;
+       entry_point_info_t *bl33_ep_info;
+       image_info_t *bl33_image_info;
+};
+
 /* Declarations for mtk_plat_common.c */
 uint32_t plat_get_spsr_for_bl32_entry(void);
 uint32_t plat_get_spsr_for_bl33_entry(void);
index 32f015721dfc54c4878b49e9208bc89078e4bfe8..d9577a6fccb528763bda3392daf5d7ffef6462bb 100644 (file)
@@ -4,7 +4,6 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 #include <arch_helpers.h>
-#include <arm_gic.h>
 #include <assert.h>
 #include <bl_common.h>
 #include <cci.h>
@@ -172,16 +171,15 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
  * BL2 has flushed this information to memory, so we are guaranteed to pick up
  * good data.
  ******************************************************************************/
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
-                                                void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+                               u_register_t arg2, u_register_t arg3)
 {
-       struct mtk_bl_param_t *pmtk_bl_param =
-       (struct mtk_bl_param_t *)from_bl2;
+       struct mtk_bl_param_t *pmtk_bl_param = (struct mtk_bl_param_t *)arg0;
        struct atf_arg_t *teearg;
        unsigned long long normal_base;
        unsigned long long atf_base;
 
-       assert(from_bl2 != NULL);
+       assert(pmtk_bl_param != NULL);
        /*
         * Mediatek preloader(i.e, BL2) is in 32 bit state, high 32bits
         * of 64 bit GP registers are UNKNOWN if CPU warm reset from 32 bit
@@ -190,8 +188,6 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
         */
        pmtk_bl_param =
        (struct mtk_bl_param_t *)((uint64_t)pmtk_bl_param & 0x00000000ffffffff);
-       plat_params_from_bl2 =
-       (void *)((uint64_t)plat_params_from_bl2 & 0x00000000ffffffff);
 
        teearg  = (struct atf_arg_t *)pmtk_bl_param->tee_info_addr;
 
@@ -445,6 +441,6 @@ void bl31_prepare_kernel_entry(uint64_t k32_64)
        INFO("BL3-1: Next image address = 0x%llx\n",
                (unsigned long long) next_image_info->pc);
        INFO("BL3-1: Next image spsr = 0x%x\n", next_image_info->spsr);
-       cm_init_context(read_mpidr_el1(), next_image_info);
+       cm_init_my_context(next_image_info);
        cm_prepare_el3_exit(image_type);
 }
index 48bf28f9cd318f45eb9925393358b804a41676c1..7485647f3f518b10fecd4765d66858367280c4a2 100644 (file)
@@ -5,7 +5,6 @@
  */
 
 #include <cci.h>
-#include <gic_v2.h>
 #include <platform_def.h>
 
 .section .rodata.gic_reg_name, "aS"
index 0fa63a1a6482eb66409da0a836bf18d951fff3d3..0110e192dc8a57a3dea88780224a30dd5a0e7365 100644 (file)
 
 #define FIQ_SMP_CALL_SGI  MT_IRQ_SEC_SGI_5
 
-#define PLAT_ARM_G0_IRQS       FIQ_SMP_CALL_SGI
-
-#define DEBUG_XLAT_TABLE 0
-
 /*******************************************************************************
  * Platform binary types for linking
  ******************************************************************************/
  ******************************************************************************/
 
 /* Size of cacheable stacks */
-#if DEBUG_XLAT_TABLE
-#define PLATFORM_STACK_SIZE 0x800
-#elif defined(IMAGE_BL1)
+#if defined(IMAGE_BL1)
 #define PLATFORM_STACK_SIZE 0x440
 #elif defined(IMAGE_BL2)
 #define PLATFORM_STACK_SIZE 0x400
 #endif
 
 #define FIRMWARE_WELCOME_STR    "Booting Trusted Firmware\n"
-#if ENABLE_PLAT_COMPAT
-#define PLATFORM_MAX_AFFLVL     MPIDR_AFFLVL2
-#else
 #define PLAT_MAX_PWR_LVL        U(2) /* MPIDR_AFFLVL2 */
-#endif
+
+#define PLAT_MAX_RET_STATE     U(1)
+#define PLAT_MAX_OFF_STATE     U(2)
 
 #define PLATFORM_CACHE_LINE_SIZE      64
 #define PLATFORM_SYSTEM_COUNT         1
 /*******************************************************************************
  * Platform specific page table and MMU setup constants
  ******************************************************************************/
-#define ADDR_SPACE_SIZE   (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE   (1ULL << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE    (1ULL << 32)
 #define MAX_XLAT_TABLES   7
 #define MAX_MMAP_REGIONS  16
 
index 47a23dfe150603386adbafe6bb7dce1ef9a7d004..11282fc546970118590a391eaa12605fa418ec81 100644 (file)
@@ -1,23 +1,24 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <gicv2.h>
-#include <plat_arm.h>
+#include <interrupt_props.h>
 #include <platform.h>
 #include <platform_def.h>
 
-const unsigned int g0_interrupt_array[] = {
-       PLAT_ARM_G0_IRQS
+static const interrupt_prop_t g0_interrupt_props[] = {
+       INTR_PROP_DESC(FIQ_SMP_CALL_SGI, GIC_HIGHEST_SEC_PRIORITY,
+                      GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
 };
 
 gicv2_driver_data_t arm_gic_data = {
        .gicd_base = BASE_GICD_BASE,
        .gicc_base = BASE_GICC_BASE,
-       .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
-       .g0_interrupt_array = g0_interrupt_array,
+       .interrupt_props = g0_interrupt_props,
+       .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
 };
 
 void plat_mt_gic_driver_init(void)
index bd47bd8b1ce172345e0d95e32269a840473e5727..d0506645f47457b8d093a8881002fd8ea148a396 100644 (file)
@@ -5,7 +5,6 @@
  */
 
 #include <arch_helpers.h>
-#include <arm_gic.h>
 #include <assert.h>
 #include <bakery_lock.h>
 #include <cci.h>
index 1bdf30af341778787f800c97a0877874e1439c05..c2fd511e66ec11358f3e326b592e0c2c8351a14d 100644 (file)
@@ -26,7 +26,8 @@ PLAT_INCLUDES         :=      -I${MTK_PLAT}/common/                           \
                                -Iinclude/common/tbbr/                                  \
                                ${OEMS_INCLUDES}
 
-PLAT_BL_COMMON_SOURCES :=      lib/aarch64/xlat_tables.c                       \
+PLAT_BL_COMMON_SOURCES :=      lib/xlat_tables/aarch64/xlat_tables.c                   \
+                               lib/xlat_tables/xlat_tables_common.c                    \
                                plat/common/plat_gic.c
 
 BL31_SOURCES           +=      drivers/arm/cci/cci.c                           \
@@ -35,7 +36,7 @@ BL31_SOURCES          +=      drivers/arm/cci/cci.c                           \
                                drivers/arm/gic/v2/gicv2_main.c                 \
                                drivers/arm/gic/v2/gicv2_helpers.c              \
                                plat/common/plat_gicv2.c                        \
-                               drivers/console/console.S                       \
+                               drivers/console/aarch64/console.S               \
                                drivers/delay_timer/delay_timer.c               \
                                lib/cpus/aarch64/cortex_a53.S                   \
                                ${MTK_PLAT_SOC}/bl31_plat_setup.c               \
@@ -52,11 +53,6 @@ BL31_SOURCES         +=      drivers/arm/cci/cci.c                           \
                                ${MTK_PLAT_SOC}/scu.c           \
                                ${OEMS_SOURCES}
 
-# Flag used by the MTK_platform port to determine the version of ARM GIC
-# architecture to use for interrupt management in EL3.
-ARM_GIC_ARCH           :=      2
-$(eval $(call add_define,ARM_GIC_ARCH))
-
 # Enable workarounds for selected Cortex-A53 erratas.
 ERRATA_A53_826319      :=      1
 ERRATA_A53_836870      :=      1
index 3e0b4f428980ef822d1f208946932f55fab3b667..d5894991db39eecaefc8b2aa8821bc8d0a8904e1 100644 (file)
@@ -36,7 +36,6 @@ func platform_is_primary_cpu
        ret
 endfunc platform_is_primary_cpu
 
-#if !ENABLE_PLAT_COMPAT
        /* -----------------------------------------------------
         * unsigned int plat_my_core_pos(void);
         *
@@ -50,7 +49,6 @@ func plat_my_core_pos
        add     x0, x1, x0, LSR #6
        ret
 endfunc plat_my_core_pos
-#endif
 
        /* ---------------------------------------------
         * int plat_crash_console_init(void)
index 996344d2cc8f5e74e3329324badbd5326336ea22..a7619926a1afc90f53ba9dc34d7f2c8b4a09f69e 100644 (file)
@@ -4,7 +4,6 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 #include <arch_helpers.h>
-#include <arm_gic.h>
 #include <bl_common.h>
 #include <cci.h>
 #include <debug.h>
index e51bdbb9ea60cefe33930808fe71fcd20ccc79f7..ce5230963f99e522ece1a19cd483a3f8ba7bfd2c 100644 (file)
@@ -12,6 +12,7 @@
 #include <mcucfg.h>
 #include <mmio.h>
 #include <mtcmos.h>
+#include <mtk_plat_common.h>
 #include <plat_arm.h>
 #include <plat_private.h>
 #include <platform.h>
@@ -91,19 +92,21 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
  * BL2 has flushed this information to memory, so we are guaranteed to pick up
  * good data.
  ******************************************************************************/
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
-                              void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+                               u_register_t arg2, u_register_t arg3)
 {
+       struct mtk_bl31_params *arg_from_bl2 = (struct mtk_bl31_params *)arg0;
+
        console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE);
 
        VERBOSE("bl31_setup\n");
 
-       assert(from_bl2 != NULL);
-       assert(from_bl2->h.type == PARAM_BL31);
-       assert(from_bl2->h.version >= VERSION_1);
+       assert(arg_from_bl2 != NULL);
+       assert(arg_from_bl2->h.type == PARAM_BL31);
+       assert(arg_from_bl2->h.version >= VERSION_1);
 
-       bl32_ep_info = *from_bl2->bl32_ep_info;
-       bl33_ep_info = *from_bl2->bl33_ep_info;
+       bl32_ep_info = *arg_from_bl2->bl32_ep_info;
+       bl33_ep_info = *arg_from_bl2->bl33_ep_info;
 }
 
 /*******************************************************************************
@@ -120,11 +123,6 @@ void bl31_platform_setup(void)
        plat_arm_gic_driver_init();
        plat_arm_gic_init();
 
-#if ENABLE_PLAT_COMPAT
-       /* Topologies are best known to the platform. */
-       mt_setup_topology();
-#endif
-
        /* Initialize spm at boot time */
        spm_boot_init();
 }
index 6e3f4a3b42c09870941dca5a01e63b42f61a5fa2..9bbed3c3b9c17b856969fc490af566998193f3d5 100644 (file)
 #define FIRMWARE_WELCOME_STR           "Booting Trusted Firmware\n"
 
 #define PLATFORM_MAX_AFFLVL            MPIDR_AFFLVL2
-#if !ENABLE_PLAT_COMPAT
 #define PLAT_MAX_PWR_LVL               U(2)
 #define PLAT_MAX_RET_STATE             U(1)
 #define PLAT_MAX_OFF_STATE             U(2)
-#endif
 #define PLATFORM_SYSTEM_COUNT          1
 #define PLATFORM_CLUSTER_COUNT         2
 #define PLATFORM_CLUSTER0_CORE_COUNT   4
index c955d618403e78be8e76fe41ac8763a362733b38..16e36afbf7afe6f515b6640c05a868655ea64dd2 100644 (file)
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#include <arm_gic.h>
+
 #include <bl_common.h>
 #include <mt8173_def.h>
 #include <utils.h>
index bc89ad92799e453bda9fa5eb541f5b70a3207f77..b19d3f307c6e31f9ec804046eb4db72ea4f3d45a 100644 (file)
@@ -26,7 +26,6 @@
 #include <spm_mcdi.h>
 #include <spm_suspend.h>
 
-#if !ENABLE_PLAT_COMPAT
 #define MTK_PWR_LVL0   0
 #define MTK_PWR_LVL1   1
 #define MTK_PWR_LVL2   2
@@ -36,7 +35,6 @@
 #define MTK_CLUSTER_PWR_STATE(state)   (state)->pwr_domain_state[MTK_PWR_LVL1]
 #define MTK_SYSTEM_PWR_STATE(state)    ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) ?\
                        (state)->pwr_domain_state[MTK_PWR_LVL2] : 0)
-#endif
 
 #if PSCI_EXTENDED_STATE_ID
 /*
@@ -234,59 +232,6 @@ static void mt_platform_restore_context(unsigned long mpidr)
        mt_cpu_restore(mpidr);
 }
 
-#if ENABLE_PLAT_COMPAT
-/*******************************************************************************
-* Private function which is used to determine if any platform actions
-* should be performed for the specified affinity instance given its
-* state. Nothing needs to be done if the 'state' is not off or if this is not
-* the highest affinity level which will enter the 'state'.
-*******************************************************************************/
-static int32_t plat_do_plat_actions(unsigned int afflvl, unsigned int state)
-{
-       unsigned int max_phys_off_afflvl;
-
-       assert(afflvl <= MPIDR_AFFLVL2);
-
-       if (state != PSCI_STATE_OFF)
-               return -EAGAIN;
-
-       /*
-        * Find the highest affinity level which will be suspended and postpone
-        * all the platform specific actions until that level is hit.
-        */
-       max_phys_off_afflvl = psci_get_max_phys_off_afflvl();
-       assert(max_phys_off_afflvl != PSCI_INVALID_DATA);
-       if (afflvl != max_phys_off_afflvl)
-               return -EAGAIN;
-
-       return 0;
-}
-
-/*******************************************************************************
- * MTK_platform handler called when an affinity instance is about to enter
- * standby.
- ******************************************************************************/
-static void plat_affinst_standby(unsigned int power_state)
-{
-       unsigned int target_afflvl;
-
-       /* Sanity check the requested state */
-       target_afflvl = psci_get_pstate_afflvl(power_state);
-
-       /*
-        * It's possible to enter standby only on affinity level 0 i.e. a cpu
-        * on the MTK_platform. Ignore any other affinity level.
-        */
-       if (target_afflvl == MPIDR_AFFLVL0) {
-               /*
-                * Enter standby state. dsb is good practice before using wfi
-                * to enter low power states.
-                */
-               dsb();
-               wfi();
-       }
-}
-#else
 static void plat_cpu_standby(plat_local_state_t cpu_state)
 {
        unsigned int scr;
@@ -298,47 +243,11 @@ static void plat_cpu_standby(plat_local_state_t cpu_state)
        wfi();
        write_scr_el3(scr);
 }
-#endif
 
 /*******************************************************************************
  * MTK_platform handler called when an affinity instance is about to be turned
  * on. The level and mpidr determine the affinity instance.
  ******************************************************************************/
-#if ENABLE_PLAT_COMPAT
-static int plat_affinst_on(unsigned long mpidr,
-                   unsigned long sec_entrypoint,
-                   unsigned int afflvl,
-                   unsigned int state)
-{
-       int rc = PSCI_E_SUCCESS;
-       unsigned long cpu_id;
-       unsigned long cluster_id;
-       uintptr_t rv;
-
-       /*
-        * It's possible to turn on only affinity level 0 i.e. a cpu
-        * on the MTK_platform. Ignore any other affinity level.
-        */
-       if (afflvl != MPIDR_AFFLVL0)
-               return rc;
-
-       cpu_id = mpidr & MPIDR_CPU_MASK;
-       cluster_id = mpidr & MPIDR_CLUSTER_MASK;
-
-       if (cluster_id)
-               rv = (uintptr_t)&mt8173_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw;
-       else
-               rv = (uintptr_t)&mt8173_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw;
-
-       mmio_write_32(rv, sec_entrypoint);
-       INFO("mt_on[%ld:%ld], entry %x\n",
-               cluster_id, cpu_id, mmio_read_32(rv));
-
-       spm_hotplug_on(mpidr);
-
-       return rc;
-}
-#else
 static uintptr_t secure_entrypoint;
 
 static int plat_power_domain_on(unsigned long mpidr)
@@ -363,7 +272,6 @@ static int plat_power_domain_on(unsigned long mpidr)
        spm_hotplug_on(mpidr);
        return rc;
 }
-#endif
 
 /*******************************************************************************
  * MTK_platform handler called when an affinity instance is about to be turned
@@ -377,30 +285,6 @@ static int plat_power_domain_on(unsigned long mpidr)
  * dealt with. So do not write & read global variables across calls. It will be
  * wise to do flush a write to the global to prevent unpredictable results.
  ******************************************************************************/
-#if ENABLE_PLAT_COMPAT
-static void plat_affinst_off(unsigned int afflvl, unsigned int state)
-{
-       unsigned long mpidr = read_mpidr_el1();
-
-       /* Determine if any platform actions need to be executed. */
-       if (plat_do_plat_actions(afflvl, state) == -EAGAIN)
-               return;
-
-       /* Prevent interrupts from spuriously waking up this cpu */
-       gicv2_cpuif_disable();
-
-       spm_hotplug_off(mpidr);
-
-       trace_power_flow(mpidr, CPU_DOWN);
-
-       if (afflvl != MPIDR_AFFLVL0) {
-               /* Disable coherency if this cluster is to be turned off */
-               plat_cci_disable();
-
-               trace_power_flow(mpidr, CLUSTER_DOWN);
-       }
-}
-#else
 static void plat_power_domain_off(const psci_power_state_t *state)
 {
        unsigned long mpidr = read_mpidr_el1();
@@ -419,7 +303,6 @@ static void plat_power_domain_off(const psci_power_state_t *state)
                trace_power_flow(mpidr, CLUSTER_DOWN);
        }
 }
-#endif
 
 /*******************************************************************************
  * MTK_platform handler called when an affinity instance is about to be
@@ -433,51 +316,6 @@ static void plat_power_domain_off(const psci_power_state_t *state)
  * dealt with. So do not write & read global variables across calls. It will be
  * wise to do flush a write to the global to prevent unpredictable results.
  ******************************************************************************/
-#if ENABLE_PLAT_COMPAT
-static void plat_affinst_suspend(unsigned long sec_entrypoint,
-                         unsigned int afflvl,
-                         unsigned int state)
-{
-       unsigned long mpidr = read_mpidr_el1();
-       unsigned long cluster_id;
-       unsigned long cpu_id;
-       uintptr_t rv;
-
-       /* Determine if any platform actions need to be executed. */
-       if (plat_do_plat_actions(afflvl, state) == -EAGAIN)
-               return;
-
-       cpu_id = mpidr & MPIDR_CPU_MASK;
-       cluster_id = mpidr & MPIDR_CLUSTER_MASK;
-
-       if (cluster_id)
-               rv = (uintptr_t)&mt8173_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw;
-       else
-               rv = (uintptr_t)&mt8173_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw;
-
-       mmio_write_32(rv, sec_entrypoint);
-
-       if (afflvl < MPIDR_AFFLVL2)
-               spm_mcdi_prepare_for_off_state(mpidr, afflvl);
-
-       if (afflvl >= MPIDR_AFFLVL0)
-               mt_platform_save_context(mpidr);
-
-       /* Perform the common cluster specific operations */
-       if (afflvl >= MPIDR_AFFLVL1) {
-               /* Disable coherency if this cluster is to be turned off */
-               plat_cci_disable();
-       }
-
-       if (afflvl >= MPIDR_AFFLVL2) {
-               disable_scu(mpidr);
-               generic_timer_backup();
-               spm_system_suspend();
-               /* Prevent interrupts from spuriously waking up this cpu */
-               gicv2_cpuif_disable();
-       }
-}
-#else
 static void plat_power_domain_suspend(const psci_power_state_t *state)
 {
        unsigned long mpidr = read_mpidr_el1();
@@ -517,7 +355,6 @@ static void plat_power_domain_suspend(const psci_power_state_t *state)
                gicv2_cpuif_disable();
        }
 }
-#endif
 
 /*******************************************************************************
  * MTK_platform handler called when an affinity instance has just been powered
@@ -526,28 +363,6 @@ static void plat_power_domain_suspend(const psci_power_state_t *state)
  * was turned off prior to wakeup and do what's necessary to setup it up
  * correctly.
  ******************************************************************************/
-#if ENABLE_PLAT_COMPAT
-static void plat_affinst_on_finish(unsigned int afflvl, unsigned int state)
-{
-       unsigned long mpidr = read_mpidr_el1();
-
-       /* Determine if any platform actions need to be executed. */
-       if (plat_do_plat_actions(afflvl, state) == -EAGAIN)
-               return;
-
-       /* Perform the common cluster specific operations */
-       if (afflvl >= MPIDR_AFFLVL1) {
-               /* Enable coherency if this cluster was off */
-               plat_cci_enable();
-               trace_power_flow(mpidr, CLUSTER_UP);
-       }
-
-       /* Enable the gic cpu interface */
-       gicv2_cpuif_enable();
-       gicv2_pcpu_distif_init();
-       trace_power_flow(mpidr, CPU_UP);
-}
-#else
 void mtk_system_pwr_domain_resume(void);
 
 static void plat_power_domain_on_finish(const psci_power_state_t *state)
@@ -574,44 +389,12 @@ static void plat_power_domain_on_finish(const psci_power_state_t *state)
        gicv2_pcpu_distif_init();
        trace_power_flow(mpidr, CPU_UP);
 }
-#endif
 
 /*******************************************************************************
  * MTK_platform handler called when an affinity instance has just been powered
  * on after having been suspended earlier. The level and mpidr determine the
  * affinity instance.
  ******************************************************************************/
-#if ENABLE_PLAT_COMPAT
-static void plat_affinst_suspend_finish(unsigned int afflvl, unsigned int state)
-{
-       unsigned long mpidr = read_mpidr_el1();
-
-       /* Determine if any platform actions need to be executed. */
-       if (plat_do_plat_actions(afflvl, state) == -EAGAIN)
-               return;
-
-       if (afflvl >= MPIDR_AFFLVL2) {
-               /* Enable the gic cpu interface */
-               plat_arm_gic_init();
-               spm_system_suspend_finish();
-               enable_scu(mpidr);
-       }
-
-       /* Perform the common cluster specific operations */
-       if (afflvl >= MPIDR_AFFLVL1) {
-               /* Enable coherency if this cluster was off */
-               plat_cci_enable();
-       }
-
-       if (afflvl >= MPIDR_AFFLVL0)
-               mt_platform_restore_context(mpidr);
-
-       if (afflvl < MPIDR_AFFLVL2)
-               spm_mcdi_finish_for_on_state(mpidr, afflvl);
-
-       gicv2_pcpu_distif_init();
-}
-#else
 static void plat_power_domain_suspend_finish(const psci_power_state_t *state)
 {
        unsigned long mpidr = read_mpidr_el1();
@@ -642,15 +425,7 @@ static void plat_power_domain_suspend_finish(const psci_power_state_t *state)
 
        gicv2_pcpu_distif_init();
 }
-#endif
 
-#if ENABLE_PLAT_COMPAT
-static unsigned int plat_get_sys_suspend_power_state(void)
-{
-       /* StateID: 0, StateType: 1(power down), PowerLevel: 2(system) */
-       return psci_make_powerstate(0, 1, 2);
-}
-#else
 static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state)
 {
        assert(PLAT_MAX_PWR_LVL >= 2);
@@ -658,7 +433,6 @@ static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state)
        for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
                req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF;
 }
-#endif
 
 /*******************************************************************************
  * MTK handlers to shutdown/reboot the system
@@ -690,7 +464,6 @@ static void __dead2 plat_system_reset(void)
        panic();
 }
 
-#if !ENABLE_PLAT_COMPAT
 #if !PSCI_EXTENDED_STATE_ID
 static int plat_validate_power_state(unsigned int power_state,
                                        psci_power_state_t *req_state)
@@ -775,34 +548,7 @@ void mtk_system_pwr_domain_resume(void)
 
        plat_arm_gic_init();
 }
-#endif
-
-#if ENABLE_PLAT_COMPAT
-/*******************************************************************************
- * Export the platform handlers to enable psci to invoke them
- ******************************************************************************/
-static const plat_pm_ops_t plat_plat_pm_ops = {
-       .affinst_standby                = plat_affinst_standby,
-       .affinst_on                     = plat_affinst_on,
-       .affinst_off                    = plat_affinst_off,
-       .affinst_suspend                = plat_affinst_suspend,
-       .affinst_on_finish              = plat_affinst_on_finish,
-       .affinst_suspend_finish         = plat_affinst_suspend_finish,
-       .system_off                     = plat_system_off,
-       .system_reset                   = plat_system_reset,
-       .get_sys_suspend_power_state    = plat_get_sys_suspend_power_state,
-};
 
-/*******************************************************************************
- * Export the platform specific power ops & initialize the mtk_platform power
- * controller
- ******************************************************************************/
-int platform_setup_pm(const plat_pm_ops_t **plat_ops)
-{
-       *plat_ops = &plat_plat_pm_ops;
-       return 0;
-}
-#else
 static const plat_psci_ops_t plat_plat_pm_ops = {
        .cpu_standby                    = plat_cpu_standby,
        .pwr_domain_on                  = plat_power_domain_on,
@@ -852,4 +598,3 @@ plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
 
        return target;
 }
-#endif
index 5bb0451dcea9db58b82af29708c476d19aeaaf57..d70fea52299ed01fbc72f0d7116f1da0e5a6d074 100644 (file)
@@ -7,31 +7,6 @@
 #include <platform_def.h>
 #include <psci.h>
 
-#if ENABLE_PLAT_COMPAT
-unsigned int plat_get_aff_count(unsigned int aff_lvl, unsigned long mpidr)
-{
-       /* Report 1 (absent) instance at levels higher that the cluster level */
-       if (aff_lvl > MPIDR_AFFLVL1)
-               return PLATFORM_SYSTEM_COUNT;
-
-       if (aff_lvl == MPIDR_AFFLVL1)
-               return PLATFORM_CLUSTER_COUNT;
-
-       return mpidr & 0x100 ? PLATFORM_CLUSTER1_CORE_COUNT :
-                              PLATFORM_CLUSTER0_CORE_COUNT;
-}
-
-unsigned int plat_get_aff_state(unsigned int aff_lvl, unsigned long mpidr)
-{
-       return aff_lvl <= MPIDR_AFFLVL2 ? PSCI_AFF_PRESENT : PSCI_AFF_ABSENT;
-}
-
-int mt_setup_topology(void)
-{
-       /* [TODO] Make topology configurable via SCC */
-       return 0;
-}
-#else
 
 const unsigned char mtk_power_domain_tree_desc[] = {
        /* No of root nodes */
@@ -82,4 +57,3 @@ int plat_core_pos_by_mpidr(u_register_t mpidr)
 
        return (cpu_id + (cluster_id * 4));
 }
-#endif
index 2eef81bb9e16ea30bddf0a05b8250f35230bd374..294aea4f8b3606d982ef8056536f1fe19c5eda4f 100644 (file)
@@ -56,11 +56,6 @@ BL31_SOURCES         +=      drivers/arm/cci/cci.c                           \
                                ${MTK_PLAT_SOC}/power_tracer.c                  \
                                ${MTK_PLAT_SOC}/scu.c
 
-# Flag used by the MTK_platform port to determine the version of ARM GIC
-# architecture to use for interrupt management in EL3.
-ARM_GIC_ARCH           :=      2
-$(eval $(call add_define,ARM_GIC_ARCH))
-
 # Enable workarounds for selected Cortex-A53 erratas.
 ERRATA_A53_826319      :=      1
 ERRATA_A53_836870      :=      1